In Thesis, we develop products using various MCUs – Cypress PSoC4/5/6, STM32, Nordic nRF, Arduino, and PIC. In the past, we did that because of various client requirements and/or outcomes from our in-depth engineering evaluation. However, we do it nowadays because we aim to make our product design as MCU agnostic as possible to circumvent supply shortages. To support this approach, we always approach our embedded firmware development in an agnostic manner, allowing easier porting to various MCUs. As a result, we utilise various IDEs daily, e.g. PSoC creator, Keil uVision, Eclipse, Visual Studio, Arduino IDE and Segger Embedded Studio.
Arduino IDE
One of the most popular IDE for firmware development right now is the Arduino IDE. However, you are only limited to board support on Arduino boards or compatible boards. Recently, Arduino officially released their Arduino 2.0 IDE with better functionalities. Most crucially, the ability to do inline debugging (https://docs.arduino.cc/software/ide-v2/tutorials/ide-v2-debugger). We believe that we speak the mind of many that one of the most frustrating aspects of IDE 1.x is the lack of inline debugging. We have to code serial output to check the serial printout, which is very time-consuming. As a result, we shifted to Microsoft Visual Studio in the early days. Nonetheless, inline debugging is not perfect because a) limited to a selective range of Arduino boards and b) requires an external debugger. However, it remains so for IDE 2.0, but at least you now have an alternative. Have you tried the new IDE? You may want to check the hackaday article out for their introduction of the IDE. https://hackaday.com/2022/09/28/arduino-ide-2-0-is-here/
Other IDEs
If you prefer a more one-size-fits-all solution (where one IDE supports multiple MCUs), Keil and Segger embedded studio (SES) are doing a remarkable job. However, such a solution is not free and can be expensive to upkeep. At this time, SES is free only if you use it on Nordic nRF series MCUs.
Our recommendation
Our recommendation is for the client or starting developer to start with the IDE recommended by the MCU SDK’s example projects. The recommendation also tends to be free.
Speak to us if you need help with your embedded product and how we can keep your design MCU agnostic to circumvent supply shock. For some of our past projects, please visit www.onethesis.com/works/.
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There is increasing public concern that adverse health effects may arise from exposure to radiofrequency (RF) sources, particularly due to the increasing use of mobile and wearable devices with growing radio-communication capabilities such as GSM, Wi-Fi, and Bluetooth. This is particularly true with wearables, which are usually worn on the body and sometimes in direct contact with the. The primary concern is that the RF electromagnetic fields can be absorbed by tissues of the human body and could potentially lead to carcinogenic or adverse health effects [1].
Since then, dozens of studies have been done to investigate the possible adverse effects of radio-communication devices near the human body with various review articles published. Specific absorption rate (SAR) is a measure of energy absorption by the body from the source being measured when exposed to a transmitting source [2, 3], which is defined as the power absorbed per mass of tissue. It has units of watts per kilogram (W/kg) and the value is averaged either over the whole body or overstated volume or mass (typically 10g of tissue). SAR provides a straightforward means for measuring the RF exposure characteristics of devices, which in most studies are usually mobile phones, due to the increasing prevalence of mobile smartphones.
Studies in 1998 hypothesize possible effects when the transmitter is in close proximity to the head (brain) [4]. However new studies done with Bluetooth transmission at 2.45Ghz with a 100mW normalized radiation power showed SAR values averaging at 0.4W/Kg [5], and 10µW/kg over 24 hours [6] – all well below ICNIRP limits of 2W/Kg [7] and FCC limits of 1.6W/Kg [8]. The results of epidemiological studies on mobile phones or broadcasting stations are inconclusive or have no known direct ill health effects on humans [1, 4-6, 9-24].
Noting public concerns and understanding of academic studies investigating the health effects of radiating devices thus far, the Federal Communications Commission (FCC)’s 47 C.F.R. 1.1307(b), 1.1310, 2.1091, 2.1093 guidelines require that smartphones sold have a SAR level at or below 1.6W/kg taken over the volume containing a mass of 1g of tissue that is absorbing the most signal [8, 12]. The European Union’s CENELEC specifies SAR limits within the region, following IEC 62209-1 [25] standards. For mobile phones and other handheld devices, the SAR limit is 2 W/kg averaged over the 10g of tissue absorbing the most signal.
The SARs for the iPhone 6 models can be found here, whilst future mobile and wearable devices complying with the emission power and SAR value not exceeding 1.6W/Kg would be a suitable design guideline [26]. A new generation of tracking and wearable technologies are designed with SAR values of <1W/Kg and will be suitable for long-term deployment in close proximity to humans.
With the explosive growth of IoT and WSNs and as the number of radio-communication devices around us increases with the increased use of wearables and reliance on smartphones, it’s important to note that safety needs to be part of a new technology of device design considerations, and over extended periods of time, and keeping RF emissions from these communication devices within acceptable limits will enable quicker regulatory approval, is socially responsible for engineers introducing new devices into the market.
References
Qing, X., et al. Characterization of RF transmission in human body. in Antennas and Propagation Society International Symposium (APSURSI), 2010 IEEE. 2010. IEEE.
EN50383, C., Basic standard for the calculation and measurement of electromagnetic field strength and SAR related to human exposure from radio base stations and fixed terminal stations for wireless telecommunication systems (110 MHz–40 GHz). Technical committee, 2002. 211.
Christ, A., et al., Characterization of the electromagnetic near-field absorption in layered biological tissue in the frequency range from 30 MHz to 6000 MHz. Physics in Medicine and Biology, 2006. 51(19): p. 4951.
Frey, A.H., Headaches from cellular telephones: are they real and what are the implications? Environmental health perspectives, 1998. 106(3): p. 101.
Pizarro, Y., et al. Specific absorption rate (SAR) in the head of Google glasses and Bluetooth user’s. in Communications (LATINCOM), 2014 IEEE Latin-America Conference on. 2014. IEEE.
Neubauer, G., et al., Feasibility of future epidemiological studies on possible health effects of mobile phone base stations. Bioelectromagnetics, 2007. 28(3): p. 224-230.
Ahlbom, A., et al., Guidelines for limiting exposure to time-varying electric, magnetic, and electromagnetic fields (up to 300 GHz). Health physics, 1998. 74(4): p. 494-521.
Fields, R.E., Evaluating compliance with FCC guidelines for human exposure to radiofrequency electromagnetic fields. 1997.
Baan, R., et al., Carcinogenicity of radiofrequency electromagnetic fields. The lancet oncology, 2011. 12(7): p. 624-626.
Bit-Babik, G., et al., Simulation of exposure and SAR estimation for adult and child heads exposed to radiofrequency energy from portable communication devices. Radiation research, 2005. 163(5): p. 580-590.
Christ, A., et al., The dependence of electromagnetic far-field absorption on body tissue composition in the frequency range from 300 MHz to 6 GHz. IEEE transactions on microwave theory and techniques, 2006. 54(5): p. 2188-2195.
Commission, F.C., Specific Absorption Rate (SAR) for Cell Phones: What It Means for You. 2014.
Kshetrimayum, R.S., Mobile phones: Bad for your health? IEEE Potentials, 2008. 27(2).
Repacholi, M.H., Low‐level exposure to radiofrequency electromagnetic fields: Health effects and research needs. Bioelectromagnetics, 1998. 19(1): p. 1-19.
Dhami, A., Studies on Cell-Phone Radiation Exposure inside a Car and near a Bluetooth Device. International Journal of Environmental Research, 2015. 9(3): p. 977-980.
See, T.S.P., et al. RF transmission in/through the human body at 915 MHz. in Antennas and Propagation Society International Symposium (APSURSI), 2010 IEEE. 2010. IEEE.
Ahlbom, A., et al., Epidemiology of health effects of radiofrequency exposure. Environmental health perspectives, 2004. 112(17): p. 1741.
De Salles, A.A., G. Bulla, and C.E.F. Rodriguez, Electromagnetic absorption in the head of adults and children due to mobile phone operation close to the head. Electromagnetic Biology and Medicine, 2006. 25(4): p. 349-360.
Faruque, M.R.I., M.T. Islam, and N. Misran, Analysis of SAR levels in human head tissues for four types of antennas with portable telephones. Australian Journal of Basic and Applied Sciences, 2011. 5(3): p. 96-107.
Beard, B.B., et al., Comparisons of computed mobile phone induced SAR in the SAM phantom to that in anatomically correct models of the human head. IEEE Transactions on Electromagnetic Compatibility, 2006. 48(2): p. 397-407.
Bernardi, P., et al., Specific absorption rate and temperature elevation in a subject exposed in the far-field of radio-frequency sources operating in the 10-900-MHz range. IEEE Transactions on Biomedical Engineering, 2003. 50(3): p. 295-304.
Christ, A., et al., Assessing human exposure to electromagnetic fields from wireless power transmission systems. Proceedings of the IEEE, 2013. 101(6): p. 1482-1493.
Christ, A. and N. Kuster, Differences in RF energy absorption in the heads of adults and children. Bioelectromagnetics, 2005. 26(S7).
Comission, I.E. IEC 62209-1:2016 Measurement procedure for the assessment of specific absorption rate of human exposure to radio frequency fields from hand-held and body-mounted wireless communication devices – Part 1: Devices used next to the ear (Frequency range of 300 MHz to 6 GHz). 2016.
Joshi, P., et al., Output Power Levels of 4G User Equipment and Implications on Realistic RF EMF Exposure Assessments. IEEE Access, 2017.
One of the ubiquitous wireless communication methods has gotten even better. Bluetooth SIG has released Bluetooth 5 (BT5), an enhancement to the current Bluetooth Low Energy v4.2. The key updates to Bluetooth 5 are 8x data, 4x range, and 2x speed, as well as improved interoperability and coexistence with other wireless technologies. For a designer and consumer, here’s what you need to know about the new BT5.
1. Eight times the data
BT5 sports a larger broadcasting capacity. The size of the message has increased from 31 to 255 octets. To be more specific, the broadcasting capacity affects only the advertising message. This is particularly useful for a beacon-like application, whereby longer sensor data can be transmitted without pairing a device.
On top of a larger broadcasting capacity, BT5 also introduced a new feature called “Advertising extensions”. This is to alleviate the possibility of the three advertising channels being over-congested, as there might exist beacon-like devices with a large broadcasting message and slow on-air transmission rate such as 125kb/s. The new feature mitigates this by keeping the shorter advertising message on the three advertising channels and offloading the longer data broadcast message to a pre-selected non-advertising channel (out of the 37 broadcasting channels). Another function of “Advertising extensions” is the ability to chain advertising packets to create a longer payload (>255 octets). This is akin to a long write, whereby a longer payload is broken down and sent via multiple max octet messages.
2. Four times the range
BLE 4.2 has a typical range of 10 to 20m and the new BT5 specification quadruples the range over which devices can transmit and receive data. In one of the demo videos from Nordic Semiconductor, a BT5 device was tested in a clear line-of-sight outdoor environment and it covered well over 770m (link)! However, there’s one caveat: the longer range the lower your data throughput.
With a longer-range coverage, this opens BT5 to a new set of potential applications and use cases. Product designers could now potentially design wireless home appliances to cover an entire house, e.g. a wireless sound bar system connected tightly to your phone regardless of the phone location within the home while keeping crisp and clear sounds wirelessly transmitting to the soundbar.
3. Twice the speed
The next major enhancement for BT5 is doubling the transmission speed from 1 to 2Mb/s while still using the same Gaussian frequency shift keying (GFSK) modulation. Coupled with advancements introduced in BLE 4.2 which allowed for Data Length Extensions (DLE), the overall throughput is 5x higher than BLE 4.0. The improved data rate means a decrease in the transmission time for data, giving designers the ability to design new applications that simply need more data throughput than was possible previously such as enabling much faster Over the Air Device Firmware Upgrades (OTA-DFU). Nordic Semiconductor has written a blog on this with a demo video to showcase the enhancement transmission speed of BT5 (link).
4. Improved operability
With the 2.4GHz ISM band getting increasingly congested, there’s always a possibility that our other 2.4GHz devices, e.g. LTE-enabled devices, get interfered or interfere with our Bluetooth device. Bluetooth SIG has introduced slot availability masks detection to prevent such interference. This feature works with the Mobile Wireless Standard (MWS) system.
Nordic Semiconductor nRF52840 Bluetooth 5-ready SoCs
THESIS now offers BT5 project development capability based on Nordic’s new nRF52840 and nRF52832 multiprotocol SoCs which are designed to take advantage of these significant performance advancements of BT5. Nordic’s nRF52840 is based on the powerful 64MHz Cortex-M4F microcontroller that meets the needs of the most demanding complex arithmetic applications such as inertial measurement (IMU) and biosensor analogue signal processing. The chip supports DSP instructions, HW accelerated Floating Point Unit (FPU) calculations, single-cycle multiply and accumulate, and hardware divide for energy-efficient processing complex operations.
The nRF52840 also has an improved output power of 8dB on top of the long-range features in BT5 and development on the nRF52840 is supported by KEIL, IAR and GCC. The chip also has a host of other power-saving features for extended battery life, a powerful on-chip cryptographic coprocessor that incorporates a true random number generator (TRNG) and support for a wide range of asymmetric, symmetric and hashing cryptographic services for secure applications and on-chip NFC.
And BT 5 is backwards-compatible with the 4.x versions. With these key improvements, BT5 is set for greater adoption in the Internet of Things (IoT) arena. New applications in the consumer home-automation space, such as controlled lighting, are possible. This is especially true for industrial IoT, where the new BT5 features are a good fit for low-data-rate sensor reading with greater range, security, and reliability.
If you’re looking for wireless technology for your IoT/smart-device project, have a chat with us to discuss the future possibilities of incorporating BT5 to speed up and simplify new product designs for your business.
We develop ideas and build solutions to solve tomorrow’s problems. Often, many come to us with promising ideas in need of technical help to develop their concepts. The challenge with idea development is that innovation initiatives frequently fail, falling short of the idealized goal. Several reasons include a lack of understanding of the steps required for a technology to reach commercialization potential and the productization stage and the lack of a simple, actionable development system or innovation strategy. The path from an idea to a fully matured technology requires several steps and processes and almost always involves prototyping steps. (see What constitutes a prototype). The innovation and development of unproven technologies take time, often entail plenty of trial and error, and almost always require a large capacity for taking risks. It is thus essential that each step concerning the development or design of novel concepts or innovative technologies is closely managed with good decisions and done so in the absence of perfect information. Step-wise, innovation execution is essential to the success of many technological projects.
Introducing the TRL scale The Technology Readiness Level (TRL) scale is a metric for describing the maturity of a technology. The scale was introduced by NASA to assess the maturity of a technology prior to integrating it into a system. It has been gaining momentum in adoption, updated, modified and used by other agencies. Most TRL guidelines are based on a scale of 1 to 9, and overtime TRL coverage has been expanded from technical indicators to include additional dimensions of readiness metrics such as hardware and software readiness, system readiness, manufacturability, and ease of integration and even commercial adoption. Further reference links are cited at the end of this article. TRLs have been defined to provide a common metric by which knowledge of new technology’s maturity might be communicated among various engineers, executives, developers and researchers, and among individuals from different organizations. Therefore, TRLs are not linked to a specific technical discipline. The use of TRLs can also provide a needed foundation for developing and communicating insight into the risks involved in advancing a new system, design and its constituent new technology components, and can also be used as a measure of risk associated with introducing new technologies into existing systems This paper considers the need for a higher TRL category, indicating a proven technology demonstrated through extended operational usage, and we have adopted a 1 to 10 scale to make it easier to understand the levels of technological development. The scale can be applied to every project involving technological development.
TRLs for Innovation and developmentLevel 1 –Observe and Report basic principles
This level encompasses ideas and hypotheses where a known fact or process is proposed for a new application. This TRL commences a transition from scientific research to applied research for the development of new technology. Fundamental investigations and paper studies commence.
Conceptual sketch of a wearable eye-movement tracking system
At this step in the maturation process, research and development (R&D) is initiated. Practical development actions can then be formulated. Applied research, theory and scientific principles are focused on a specific application area to define the concept and characteristics of the application and specified in a document where functional block diagrams are described clearly. Materials and components are procured at this stage.
CAD preliminary 3D designs of technology for visualization at TRL 2
Level 3 – Establish critical function, proof of concept
R&D work has begun. Laboratory studies aim to validate analytical predictions of separate components of the technology. This stage is also known as the “breadboarding stage” where demonstration of technical feasibility produces representative data to achieve critical function and/or characteristic proof of concept.
Electronics or necessary modules required to demonstrate critical function are done at TRL 3
Level 4 – Laboratory testing of prototype component or process
Here, the designs, development and lab testing of various components are integrated to establish that they will work together to achieve the concept-enabling levels of performance required in the final design. They should also be consistent with the requirements of potential system applications. Thus, system-level component and/or breadboard validation in a laboratory environment will identify potential design issues and corrections can be taken at this step.
Several modules/components are integrated together for characteristic testing at TRL 4
Level 5 – Alpha testing of the integrated system
The basic technological components (component level, sub-system level or system level) are integrated together with realistic supporting elements to be tested in a simulated or somewhat realistic environment. This prototype stage closely resembles the eventual system and comprises near-finalized electronics or mechanical designs. For example, a new type of solar photovoltaic controller promising higher efficiencies would, at this level, be used in an actual fabricated small-run prototype unit with actually integrated power supplies, protective enclosures, supporting structures, etc., and tested in a simulated environment for data-collection and performance evaluation.
Level 6 – Verify prototype system, begin field testing.
The prototype system is tested and demonstrated in a relevant operational environment where full-scale realistic problems will be observed. If problems arise at this stage, the design must return to TRL 5 or 4 for corrective measures depending on the severity. Engineering feasibility must be fully demonstrated in the actual system application as the design is effectively “locked-in” at this stage and optimized for manufacturability. Ready-to-manufacture (RTM) designs and documentation steps will be carried out to ensure the design is reproducible with the relevant manufacturing steps. Not all technologies will undergo a TRL 6 demonstration. At this point, the maturation step is driven more by assuring management confidence, than by R&D requirements. The demonstration might represent an actual system application, or it might be like the planned application, but using the same technologies.
Level 7 – Demonstrate integrated pilot system, start tooling and manufacturing.
The prototype is near or at the planned operational system level. The final design is virtually complete. The goal of this stage is to remove engineering and manufacturing risks. The system prototype is demonstrated in an operational environment. In this case, the prototype should be near or at the scale of the planned operational system and the demonstration must take place in the actual field environment. This level of maturity indicates system-engineering and development-management confidence. Not all technologies in all systems will go to this level. For example, solar-powered experimental weather nodes for data-gathering are deployed for extended periods of time to gather environmental data but are not slated for mass production or productization.
Level 8 – Incorporate system in commercial design
The technology has been proven to work in its final form under the expected conditions. In most cases, this level represents the end of true system development. The actual system is completed and qualified through tests and demonstration and is submitted for regulatory approvals at this stage. All commercial technologies being applied in actual systems go through TRL 8. In almost all cases, this level is the end of true “system development” for most technology elements. Most user documentation, training documentation and maintenance documentation are completed. All functionality is tested in simulated and operational scenarios. Verification and validation are completed and commercially launched or deployed en masse.
Level 9 – Deploy the system commercially.
The technology in its final form, thoroughly tested and demonstrated, is ready for commercial deployment. The actual system is proven through successful operations in a variety of conditions across a variety of end-users. In almost all cases, this is the end of “bug fixing” and is no longer considered “technology development”. Successful operational experience and sustaining and/or maintenance engineering support mechanisms are put in place.
An example of a TRL 9 is the Tesla Model S sedan vehicle, image credit: Tesla
Level 10 – Commercial Acceptance
The product, process or service has been launched commercially for an extended period, marketed to and adopted by a group of customers (including public authorities). The technology has been used without incident (or with incident levels within an acceptable range) for a protracted period of time. The technology has been certified (if applicable) via appropriate technology-type certification mechanisms, through evaluation of repeated operations and other means. Failure rates for the technology are known and failure conditions and their causes are understood. The technology/system operates without unacceptable levels of unplanned troubleshooting or repair being required.
Examples of TRL 10 are the Apple iPhone 6 and Boeing 747 aircraft.
TRL summary
An illustration of the TRL scale for increasing technology maturity, in the context of the progression from basic research to system operations.
Engineers have a wide variety of microcontrollers to choose from for various application needs. While microcontrollers have come a long way with lower power and faster clock speeds – program memory (RAM/ROM) is often still very limited. There are several reasons for this. First, memory requires a lot of silicon die area. This means that increasing the memory increases the silicon area of the chip and therefore the cost of manufacturing. Second is the issue of the manufacturing process. Different architecture require different manufacturing processes and it is not possible to send different parts of the same chip through different processes. Since RAM arrays should ideally be optimized in different ways than the rest of the chip, it is more economical to design the memory architecture to match the microcontroller, as a single silicon wafer must be manufactured with the same process to produce individual chips that will be cut out later. Semiconductor foundries which manufacture RAM chips have dedicated processes for optimizing RAM, not microcontrollers or other logic. Thus, producing RAM on a microcontroller die would mean trade-offs. Since larger RAM arrays have an increased surface area, faults are more likely to develop, simply due to the increased area. This decreases yield and increases costs. If a section within the RAM array on a microcontroller fails, the microcontroller logic must be discarded as well. The solution is to manufacture microcontroller chips separately from memory chips. If an embedded system requires more memory to hold firmware, libraries, stacks of persistent data, a solution is an external flash memory chip, such as EEPROM (Electrically Erasable Programmable Read-Only Memory), serial flash, NOR or FRAM (Ferroelectric RAM) memory chips. EEPROMs are a standard non-volatile memory, where individual bytes can be independently read, erased and re-written, and they have been dominant on the market for decades. Two other main technologies dominate the non-volatile flash memory market today – NOR and NAND. The newer form of non-volatile memory – FRAM – uses a ferroelectric layer instead of a dielectric layer which enables a higher access speed. EEPROM memory was invented in 1977 and was the mainstay for microcontroller memory till the NOR flash was introduced by Intel in 1988. The NAND flash architecture was introduced by Toshiba in 1989 and it quickly gained popularity for usage in USB thumb drives, memory cards, compact flash and solid-state memory devices (SSDs). Let’s look at some options available:
EEPROM
FRAM
NOR Flash
NAND Flash
SDcard Flash
Communication interface
SPI and I2C
SPI and I2C
Mostly SPI/Parallel
Mostly SPI/Parallel
SPI
Speed
Depending on MCU I2C – up to 1Mhz SPI – up to 16Mhz
Depending on MCU I2C – up to 1Mhz SPI – up to 16Mhz
Depending on MCU Parallel – 10MHz SPI – 100MHz
Depending on MCU Parallel – 10MHz SPI – 100MHz
Depending on MCU SPI – 100MHz
Power consumption
Low ~5mA per read/write
Very low 175µA per Read/write
High ~60-100mA
High ~15-30mA
High ~30-100mA per Read/write
Ease of use?
Easy
Easy
Relatively complex
Relatively complex
Requires FATFS
$ / byte
~S$1 / Mbit
~S$4 / Mbit
~S$8/Gbit
S$0.5/Gbit
<S$1/GB
Typical memory
~1Kb – 2Mbit ~(16 – 262 KB)
~1Kbit – 2Mbit ~(16 – 262 KB)
~1Mbit – 2Gbit
~256Mbit – 64Gbit
Very large Gigabytes+
Note
Can do byte write1 and page write
Real and instantaneous byte read/write
Supports one-byte random access
Sequential read
Sequential read
Write Cycles
~1 Million read-write cycles
100 trillion read-write cycles
~100k
~100k
~100k
1mechanism for byte write is based on page write. I.e. an entire page will be written even if just for a byte.
Read and Write Considerations
The choice between NOR and NAND depends on your application. NOR reads slightly faster than NAND, while NAND writes much faster than NOR. NAND erases two magnitudes faster than NOR (4msec vs. 5 sec), as most writes must be preceded by an erase operation, while NAND has smaller erase units for fewer erases in less time required. Further details comparing NAND and NOR flash devices are available on a white paper published here, and EETimes has published an article on this topic here. Which memory type should you choose? NOR is fundamentally a random-access memory device. It has enough address pins to map its entire storage, allowing for easy access to each of its bytes. However, NAND devices require an additional I/O interface or controller, which may vary across models and manufacturers. NAND is typically accessed in bursts of 512 bytes; i.e., 512 bytes can be read and written at a time, allowing for faster write speeds than NOR. This makes NOR ideal for running code, while NAND is best used as a data storage device (harddrive).
Power Consumption Considerations
Depending on your project applications’ needs, you might want to weigh the benefits between ultra-low power consumption and memory capacity. If the project involves wearables with limited battery capacity, or a wireless IoT-type sensor node powered by a solar panel, a low-power EEPROM/FRAM solution might be suitable. While retaining the same functionality, the advantages FRAM offers over EEPROMs and non-volatile memory are its ultra-low power usage, faster write performance (1,000x faster than EEPROM) and a practically limitless maximum number of write-erase cycles – 100 trillion read/write cycles or greater. To top it off, FRAM is also far more resistant to gamma radiation and electromagnetic fields than other memory types. However, the disadvantages of FRAM are its much lower storage densities and much higher cost. FRAM memory modules are manufactured by Cypress Semiconductor and Fujitsu as well as Texas Instruments, which is a proponent of FRAM in its MSP430 family of microcontrollers, read more here and here.
Choices
How to mitigate reduced storage densities when comparing NAND/NOR vs EEPROMs/FRAMs? The total storage capacity of FRAMs/EEPROMs is daisy-chain upgradable, although this somewhat increases cost at reduced power consumption.
Power Consumption
High
Low
Memory capacity
Low
EEPROM
FRAM
High
Flash memory (SD card / NAND-type)
NOR and NAND
Breakouts
SPI Serial Flash Memory (2Mbits) Breakout The Winbond’s W25X20CL Serial Flash Memory chip is found in the Xiaomi Miband activity tracker and comes with 2Mbits of non-volatile memory storage. There are 1024 programmable pages of 256 bytes/page via the SPI bus and it boasts a very low power consumption – 1mA (active mode) and 1µA for power down, and operates up to 104Mhz clock speed. Available from our distribution partner here.
Cypress FM24N10 FRAM breakout This has low power consumption (175µA @ 100kHz SCLK read/write operations, 5µA during sleep), high data retention (up to 151 years @ 65℃) and 100 trillion (1014) instantaneous read/write cycles (per byte). It comes in an SOIC8 package and is a direct replacement for most EEPROM parts. Available from our distribution partner here.
Micron MT25Q 256Mb, 3V, Multiple I/O Serial Flash Memory The MT25Q is a multiple input/output, 256Mb, 3V, SPI-bus Flash memory device capable of operating up to 133Mhz and it is available in multiple footprints. OEM manufacturer information – MT25QL256ABA
EEPROMs, NORs, NANDs and FRAMs are all commercially available for engineers to select from today. The newest forms of memory, known as MRAM (which is not yet widely available) and NRAM, are set to revolutionize the flash memory market in time to come with applications demanding faster read/write and lower power operations. Each project and need is unique. To learn more about how we can help you with your design, do contact us. Build the Future.
The final step in an embedded system typically occurs when the firmware or code is flashed into the micro-controller/processor on a PCB and the process almost always requires some sort of physical connection. There are two main methods of momentary contacting assembled electronics – flying probe testing (woodpecker) or a bed-of-nails test fixture.
Both methods involve pins contacting and touching the board on at least two points at a time, allowing for a variety of functional tests to be conducted and/or programmed onto the assembling chips. The difference is that a flying probe utilizes a highly accurate, coordinate-controlled machine head that pans and moves across the PCB testing various points a few pins at a time, whereas a bed-of-nails fixture looks more like an acupressure chair a fakir would use, where dozens to hundreds of pins make contact on the board at the same time.
PCB Design Considerations required
A designer will usually add test pads or programming pads in designs for in-circuit testing with a jig later in the production line.
Flying probe test machines are high-speed, expensive, professional-grade testing equipment generally used for mass-production level PCBs with very fine pitches that don’t have the luxury of test-pad real estate on the PCB. On the other hand, the more common approach will be to use a bed-of-nails test jig if tens of thousands of units are to be programmed or tested.
Test jigs can be built and customized for any type of electronics manufacturing and almost any volume of output, be it mass production or to suit small- to medium-scale electronics manufacturers. Manufacturers of test jigs usually offer both options. SPEA Automatic Test Equipment is one such manufacturer, and configurable kits are commercially available, such as the Merifix PCB test fixture.
Flashing firmware at a prototyping stage
The challenge for designers during the prototyping stage is that it will be too costly to tool a jig for a small run of uncommitted PCB designs and too time-consuming to code coordinates into an expensive flying-probe machine and a conventional approach of adding a connector to each PCB only to remove them later adds unnecessary cost and is wasteful and impractical for loading firmware en masse when the number of test boards increases for various reasons (environmental testing, alpha-user testing etc.)
Enter the electronic test fixture, also known as a jig. Jigs play a crucial role in programming electronics as well as post-assembly testing, also known as in-circuit testing (ICT), where a pogo probe or needle contacts a particular area of the assembled electronics for testing functionality or loading firmware into a chip on the board.
Testing each and every board on the manufacturing line is unavoidable, and in cases where a manufacturer produces tens of thousands of units in a day, timing is critical and automatic test jigs are capable of programming/testing and identifying/removing defective units for rectification or disposal. They can also reduce costs because they allow even non-technical people to perform the tests.
In our labs, we build test electronics on a daily basis, and testing them is just as important. Here we show make test jigs quickly on a small prototyping scale by building a jig resembling a bed-of-nails test fixture using pogo pins for customized, small-volume testing and programming.
With our completed PCB, you can now mirror the PCB design and expose all vias (un-tent) or test pads and fabricate a mirrored PCB of the layout to your specific debugging port pin-layout depending on the chip or microcontroller you may be using.
Actual electronics to be tested/programmed are placed on a mechanical holder of the jig, and the pogo bed-of-nails PCB is then lowered down to make contact with the target electronics. The entire setup will be placed inside a custom-designed 3D-printed jig, with the programming PCB wired out to the debugger interface or a programmer. The spring-loaded (pogo) pins are recommended when placing electronics on a jig and the contact points are temporary and may be uneven.
Actual electronics to be tested/programmed are placed on a mechanical holder of the jig, and the pogo bed-of-nails PCB is then lowered down to make contact with the target electronics. The entire setup will be placed inside a custom-designed 3D-printed jig, with the programming PCB wired out to the debugger interface or a programmer. The spring-loaded (pogo) pins are recommended when placing electronics on a jig and the contact points are temporary and may be uneven.
The mechanical structure of the jig is 3D-printed for quick prototyping
The pogo pins are then aligned with a dummy target board and soldered in place. (This step is optional if the design already has a PCB sandwich to align the pogo pins).
The target board is then placed in the mechanical slot designed into the jig, and the programming PCB is then mounted by other 3D-printed parts and – viola the programming-/-test jig is complete.
The various components of a jig are laid out.
There is no hard-and-fast rule in a jig design. For alignment, the programming pogo-pin interface can be sandwiched between 3D-printed parts, or two PCBs can be used for alignment. Pogo pins can be downward- or upward-facing, depending on where the test pads are or which approach is more convenient.
Another angle shows the use of two PCBs to align the pogo pins, with the pogo pins upward facing.
A 3D prototype of a jig can be designed and printed in a day, and all minor-dimension tweaks can be done right at your desk. You’ll be ready to test and program small batches of target projects quickly, painlessly and effectively. Program-test-pass, place the next target board in the jig, run the program, and so on and so forth.
One of our rapidly-prototyped jig setups connected to a programmer.
We hope you find this entry useful, do talk to our consultants to learn more about our range of services which include full turnkey design, electronics, hardware, software and full-stack firmware design.
A designer will usually add test pads or programming pads in designs for in-circuit testing with a jig later in the production line.
The mechanical structure of the jig is 3D-printed for quick prototyping
